IBM continues to advance the technology for graphene transistors for use in high-speed electronics. The company’s most recent patent application describes a transistor in which parasitic capacitance and resistance is removed by engineering the geometry of the transistor.
US patent application number 20120329260 strives to resolve the issue of parasitic capacitance and undesired resistance common to graphene field-effect transistors (FETs). The capacitance and resistance often stem from a dielectric layer which is introduced to insulate the gate from the source and drain electrodes. In IBM’s proposal, the amount of dielectric is minimized by engineering the FET geometry.
Using an unconventional approach, IBM describes a sheet of graphene with an insulator that covers a small area of the sheet. On top of that insulator is grown a metal gate, which is in turn used as a shadow mask for depositing the source and drain gates. In this way, the source and drain are separated from the top gate by a small but well controlled distance.
IBM keeps showing a clear dedication to developing ultrafast electronics based on graphene and continues to be the top firm in this direction.